1. Field of the Invention
The present invention relates generally to interconnection structures of semiconductor integrated circuit devices and a manufacturing method therefor, and more particularly to an interconnection structure of a semiconductor integrated circuit device in which multilayer aluminum interconnection layers are mutually connected through a connection hole, and to a manufacturing method therefor.
2. Description of the Prior Art
In general, a semiconductor device comprises a semiconductor substrate and elements such as transistors formed thereon. Various interconnection layers are formed on the semiconductor substrate for electrically connecting these elements to each other and to an external circuit(s). These interconnection layers have been formed of polysilicon films, high melting point metal films, high melting point metal silicide films, aluminum films and aluminum alloy films. In recent years, reduction of the interconnection layer resistance has been required in the semiconductor integrated circuit devices which are highly integrated for high speed operations. Therefore, the semiconductor integrated circuit devices essentially require aluminum multilayer interconnection structure formed of aluminum films or aluminum alloy films having a small resistivity. An example of the conventional aluminum multilayer interconnection structure is disclosed in "High Performance Multilevel Interconnection System with Stacked Interlayer Dielectrics by Plasma CVD and Bias Sputtering", M. Abe et al, pp. 404-410, VMIC conference 1989.
FIG. 6 is a partial sectional view showing an example of an aluminum multilayer interconnection structure in the conventional semiconductor integrated circuit device. In the figure, a silicon semiconductor substrate 1 bears DRAM (Dynamic Random Access Memory) cells 2 which are formed in a stacked cell structure. A base insulator film 3 is formed on the DRAM cells 2. First aluminum interconnection layers 4 are formed on the base insulator film 3 with predetermined spaces between each other. The first aluminum interconnection layers 4 are covered with an interlayer insulating film 5, which is provided with connection holes 6 (also called as "via-holes" or "through-holes"). Second aluminum interconnection layers 7 are formed on the interlayer insulating film 5 and are connected to the first aluminum interconnection layers 4 through the connection holes 6. A protection insulator film 8 is formed to cover the DRAM cell 2, first aluminum interconnection layers 4 and second aluminum interconnection layers 7 to protect them against moisture and other external material from entering.
In the conventional aluminum multilayer interconnection structure shown in FIG. 6, yield and reliability of the semiconductor device technically depend on stability of a connection part (hereinafter called "via-hole part") between the first aluminum interconnection layer and the second aluminum interconnection layer. A manufacturing method of the conventional aluminum multilayer interconnection structure shown in FIG. 6 will be described particularly with respect to formation of the via-hole part. The multilayer interconnection structure has been generally formed of a combination of polysilicon wirings, high melting point metal wirings, high melting point silicide interconnection layers and aluminum wirings. However, the following discussion is made with respect to an aluminum two-layer structure in which both interconnection layers in the first and second layers are aluminum interconnection layers.
FIGS. 7A-7G are partial sectional views showing, in accordance with manufacturing steps, a manufacturing method for the aluminum two-layer interconnection structure in the conventional semiconductor integrated circuit device.
Referring to FIG. 7A, the DRAM cell 2 is formed on a surface of the silicon semiconductor substrate 1. The DRAM cell 2 is formed of an element separator oxide film 301, a transfer gate electrode 302, an impurity diffusion layer 303, a word line 304, a memory node 305, a capacitor insulator film 306, a cell plate 307 and an insulator film 309.
Referring to FIG. 7B, the base insulator film 3 is formed on an entire surface of the silicon semiconductor substrate 1, on which the DRAM cell 2 has been formed. Then, photolithography and etching technique are used for forming a contact hole 308 at a predetermined position in the base insulator film. The first aluminum interconnection layer 4 is formed as a bit line and electrically contacts with the impurity diffusion layer 303 through this contact hole 308.
Recently, a semiconductor integrated circuit device in which sizes of elements are reduced to an order of submicron has employed the interconnection layer in which a barrier metal film 310, e.g., of titanium nitride (TiN) or titanium-tungsten (TiW) and an aluminum alloy film 311 of A -Si-Cu or others are combined. The aluminum interconnection layer having such structure has been used for the following reasons.
(1) If the aluminum is in direct contact with the silicon substrate (impurity diffusion layer) at the contact part, an abnormal reaction (i.e., alloy spike) is locally caused. This produces a reaction layer which breaks through a region of the impurity diffusion layer and extends downwardly in the silicon substrate, resulting in a junction leak at the impurity diffusion layer. In order to prevent this, the barrier metal film is formed in direct contact with the silicon substrate (impurity diffusion layer).
(2) Silicon in the aluminum alloy film is deposited at the contact part due to the solid-phase epitaxial growth, which causes imperfect contact. In order to prevent this, the barrier metal film is formed under the aluminum alloy film.
(3) Upper layers such as an interlayer insulating film and protection insulator film are formed over the aluminum interconnection layer. A film stress by these upper insulator films may break the aluminum interconnection layers. In order to increase the resistance against such stress migration phenomenon, the barrier metal film is formed under the aluminum alloy film.
A film forming the first aluminum interconnection layer 4 is usually formed by deposition in a sputter method and subsequent patterning thereof, using the photolithography and etching.
Structures in which the first aluminum interconnection layer is formed of a stacked layer structure of a titanium film, a titanium nitride film and an aluminum contained film are disclosed in the Japanese Patent Laying-Open Nos. 64-59937 (1989) and 61-90455 (1986).
Referring to FIG. 7C, the interlayer insulating film 5 is formed on the whole surface of the first aluminum interconnection layer 4. This interlayer insulating film 5 is formed of a combination of a silicon oxide film 321 formed by, e.g., the CVD (Chemical Vapor Deposition), an inorganic application insulator film 322 and a silicon oxide film 323 formed by the CVD.
The silicon oxide film 321 is formed by the CVD utilizing a heat and a plasma at a formation temperature of 300.degree.-450.degree. C., using a mixture of on one hand a silane (SiH.sub.4) gas and on the other hand an oxygen (O.sub.2) gas or a dinitrogen monoxide (N.sub.2 O) gas. Recently, a silicon oxide film has been formed from an organic silane contained material such as TEOS (Tetra-Ethyl-Ortho-Silicate) characterized by a good step coverage.
The inorganic application insulator film 322 formed for flattening generally includes silanol (Si(OH).sub.4) or the like as a main component. After rotary application of material including the silanol or the like as a main component, baking is carried out at a temperature of 400.degree.-450.degree. C. for changing it to a silicon oxide film, whereby the surface of the silicon oxide film 321 formed by the CVD is flattened. Since this inorganic application insulator film 322 has a high hygroscopic property, it may cause a disadvantage such as gas emission if the insulator film 322 is exposed at a side wall of the via-hole part. Therefore, an etchback processing using dray etching by a fluorine contained gas or argon gas is effected on this inorganic application insulator film 322 so as to prevent the exposure of the surface of the inorganic application insulator film 322 at the side wall of the via-hole part.
A silicon oxide film 323 is formed on the inorganic application insulator film 322 in a manner similar to that for forming the silicon oxide film 321.
Referring to FIG. 7D, the connection hole 6 is formed by the photolithography and etching to expose a predetermined surface area of the first aluminum interconnection layer 4. This step is carried out as follows.
A photoresist 324 is provided to cover an area except for that in which the connection hole 6 is formed by the photolithography. Then, the interlayer insulating film 5 is selectively removed by a taper etching method to open the connection hole 6. The taper etching method is a combination of wet etching by a fluorine contained solution and reactive ion etching using a mixture of gases of CHF.sub.3 and O.sub.2 as main components.
The photoresist 324 as well as a reaction product and others produced in the etching are removed by an oxygen (O.sub.2) plasma and a wet chemical processing after the etching.
Referring to FIG. 7E, in the step for forming the connection hole 6, the surface of the first aluminum interconnection layer 4 is exposed to a plasma of a fluorine contained gas such as CHF.sub.3 and/or an oxygen gas so that a deterioration layer 201 of aluminum which includes fluoride and oxide is formed at a thickness of about 100 .ANG. on the surface of the first aluminum interconnection layer 4 in the connection hole 6. Therefore, in order to remove an insulator film, i.e., the thin deterioration layer of the aluminum and to obtain a stable contact resistance, sputter etching using an argon ion (Ar.sup.+) 202 is effected prior to the formation of the second aluminum interconnection layer.
Then, as shown in FIG. 7F, the second aluminum interconnection layer 7 is continuously deposited in a vacuum, using the sputter method. This second aluminum interconnection layer 7 is a film of aluminum alloy such as Al-Si, Al-Si-Cu or Al-Cu. This film is formed by the patterning, using the photolithography and etching in a manner similar to that for the first aluminum interconnection layer.
After the formation of the second aluminum interconnection layer 7, heat treatment is carried out at a temperature of about 400.degree.-450.degree. C. so as to electrically contact the first and second aluminum interconnection layers 4 and 7 together in the connection hole 6.
Finally, as shown in FIG. 7G, the protection insulator film 8 such as a silicon oxide film or silicon nitride film is deposited on the second aluminum interconnection layer 7 by the CVD so as to protect the semiconductor elements and interconnection layers against the moisture and other entering from the external.
The aluminum multilayer interconnection structure of the prior art has the following problems.
Due to the miniaturization of the wiring, the diameter of the connection hole 6 has been reduced. If the diameter of the connection hole 6 is at a sub-micron level, a problem may be caused with respect to stability and reliability in the electrical connection at the contact hole 6.
In the prior art, as described above, the sputter etching is effected by the argon ion prior to the formation of the second aluminum interconnection layer 7. In this etching, as shown in FIG. 8A, an argon ion 202 removes a deterioration layer 201 (a layer including the fluoride and oxide of the aluminum) formed on the surface of the first aluminum interconnection layer 4 in the connection hole 6. In the conventional structure in which the contact hole 6 has a relatively small aspect ratio (B/A) less than 1 (one), wherein A is a diameter of the connection hole and B is a film thickness (about 1 .mu.m) of the interlayer insulating film, particles 203 of the oxide and the fluoride of aluminum sputtered by the argon ion 202 sufficiently scatter up to the outside of the connection hole 6, as shown in FIG. 8A. Therefore, the deterioration layer 201 of the aluminum is removed and thus the surface of the first aluminum interconnection layer 4 in the connection hole 6 can be cleaned.
However, if the connection hole 6 having the diameter at the sub-micron level and the aspect ratio (B/A) over one, as shown in FIG. 8B, the particles 203 of the oxide and fluoride of aluminum sputtered by the argon ion 202 is partially blocked by the side wall of the connection hole 6, and thus can not scatter to the outside of the connection hole 6. Therefore, some of the particles 204 re-stick onto the inside of the connection hole 6. This phenomenon is reported in "A New Reliability Problem Associated with Ar Ion Sputter Cleaning of Interconnect Vias", H. Tomioka et al, IEEE/IRPS, 1989, pp. 53-58.
As a result, even if the continuous deposition of the second aluminum interconnection layer 7 in a vacuum is carried out as a next step, the particles 204 of the oxide and fluoride of aluminum, which have stuck onto an interface 205 between the first and second aluminum interconnection layers 4 and 7 in the connection hole 6 during the sputter etching, remain there. Thereby, in the heat treatment at about 400.degree.-450.degree. C. after the formation of the second aluminum interconnection layer, mixing can not be sufficiently effected at the interface 205 between the first and second aluminum interconnection layers.
Consequently, a contact resistance (called a "via-hole resistance") in the connection hole 6 may be increased and/or an open failure, i.e., a failure in conduction between the first and second aluminum interconnection layers, may be caused.
Further, even if the initial via-hole resistance has a correct value owing to a heat treatment at 400.degree.-450.degree. C. described above, the mixing has not been sufficiently effected at the interface 205 between the first and second aluminum interconnection layers. Therefore, the reliability in the connection hole 6 such as resistance against the electro-migration and stress-migration is reduced.
These problems are and will be significant in the semiconductor integrated circuit devices which are miniaturized in the half micron order and the semiconductor integrated circuit devices which, in the future, will be miniaturized in the sub-micron order and thus will have a further increased aspect ratio (B/A).
Aspect ratio (B/A), considerations also apply to contact holes for lower wiring layers other than the aluminum and the silicon semiconductor substrate, e.g., to the contact hole 308 shown in FIG. 7B. However, a natural oxide film, deterioration layer and/or others which are formed on the surface of the contact hole 308 can be selectively removed by the cleaning processing with adequate acid or alkali such as hydrofluoric acid.
However, in the via-hole part described above, the lower wiring layer is formed of the aluminum interconnection layer having less resistance against solution of the acid and alkali. Therefore, it is impossible to employ the above described cleaning processing with the strong acid or alkaline for removing the deterioration layer and others.
The Japanese Patent Laying-Open No. 64-59937 (1989) has disclosed a Ti film which is formed at a thickness of 1000 .ANG. as a base film of the second aluminum interconnection layer. However, this Ti film easily reacts with the second aluminum interconnection layer located above it in the heat treatment after the formation of the interconnection layers, and does not sufficiently react with the lower layer, i.e., the first aluminum interconnection layer, in the connection hole. Therefore, this Ti film does not serve to promote the mixing at the interface between the first and second aluminum interconnection layers.
The Japanese Patent Laying-Open No. 61-90445 (1986) "Multilevel Interconnection for Half-Micron VLSI's", T. Nishida et al, VIMC Conference, 1989, pp. 19-25, has disclosed TiN film formed as a base film of the second aluminum interconnection layer. However, this TiN film lacks a reactivity with the aluminum interconnection layer. Therefore, this TiN film does not serve to promote the mixing at the interface between the first and second aluminum interconnection layers.